Communications systems generally require that the operation of synchronous transmission elements within the system be coordinated to some timing signal derived from a reference clock signal. The derived timing signal is synchronized, or locked, to the reference clock signal. One well-known clock synchronization technique is the use of a phase locked loop (PLL).
A PLL is a frequency-selective circuit generally containing a phase comparator, a low-pass filter, and an oscillator coupled in a feedback arrangement. When an input or reference clock signal is applied to the PLL, the phase comparator compares the phase of the reference clock signal with the phase of the oscillator output signal and generates an error signal that is related to the phase relationship between the two signals. This error signal is filtered, amplified, and applied to the oscillator, thus driving the frequency of the oscillator output signal in a direction to more closely align its phase to that of the reference clock signal. When the oscillator output frequency is sufficiently close to the reference frequency, the feedback nature of the PLL causes the oscillator output to lock to the reference clock signal frequency, with the exception of some finite phase difference. The point is called the “zero phase error.” While the phases may not be aligned, their frequencies are matched such that the amount of phase difference remains substantially constant. The self-correcting nature of the PLL thus allows the system to track the frequency changes of the reference clock signal once it is locked. A frequency divider is often inserted in the feedback loop when the desired output frequency of the oscillator is some multiple of the reference clock signal frequency.
FIG. 1 is a block diagram of a typical PLL 100. The PLL 100 includes a phase comparator 110 having a first input for the reference clock signal and a second input for the feedback signal. The output of the phase comparator 110 is coupled to the input of a loop filter 120. The output of the loop filter 120 is coupled to the input of an oscillator 130 for providing the control signal to the oscillator 130. The oscillator 130 is often a voltage-controlled oscillator (VCO) or a digitally-controlled or numerically-controlled oscillator (NCO). An NCO generally includes a fixed-frequency oscillator and a synthesizer for providing a scaled output signal derived from a reference frequency of the fixed-frequency oscillator. The output of the oscillator 130 is fed back to the second input of the phase comparator 110 through a frequency divider 140.
Crystal oscillators are generally used in precision PLLs. These oscillators are preferred due to their high accuracy. Such oscillators are capable of maintaining a frequency within 1 ppm of the desired frequency. However, crystal oscillators may be prone to long-term drift.
In communications systems, the timing signal must be maintained, even if the reference clock signal is lost or degraded, in order to avoid loss of transmission data. A holdover signal may be applied to the oscillator as a control signal in the event the PLL goes open-loop, i.e., the PLL loses its reference clock signal, or otherwise enters an impaired operating condition due to degradation of the reference clock signal. The holdover signal is the expected control signal necessary to produce the desired frequency of the timing signal.
Communication systems generally make use of a hierarchy of timing sources. These timing sources have quality levels that are often defined in terms of strata. Each stratum level has, among other requirements, a defined maximum drift as a fractional frequency offset. For example, a Stratum 1 clock is a primary reference source. Such primary reference sources may be autonomous timing sources or they may generate their timing signal from an external reference clock signal. Stratum 1 clocks have a drift of 10−11 or less. A Stratum 2 clock tracks a reference clock signal (such as a Stratum 1 signal) under normal operations and maintains its frequency in holdover conditions. Stratum 2 clocks have a maximum drift of 10−10 per day in the absence of the reference clock signal. A Stratum 3E (Stratum 3 Enhanced) clock tracks a reference clock signal (such as a Stratum 1 or Stratum 2 signal) under normal operations and maintains its frequency in holdover. Stratum 3E clocks have a maximum drift of 10−8 per day in the absence of the reference clock signal. Additional requirements and strata are known, as well as other industry-recognized quality levels.
Timing sources of the type described above generally provide information regarding their stratum level or other quality characteristics. As an example, the Synchronization Status Message (SSM) of Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) formats uses a portion of each carrier signal to indicate the acceptability status and quality level of the signal. SSMs relay information regarding the quality level of the timing signal provided by a network element. Downstream elements pass this upstream timing information to subsequent nodes. While SSMs were originally used to pass information between network elements within the frame overhead, it is not uncommon to have this information passed through to a Building Integrated Timing Supply (BITS)/Synchronization Supply Unit (SSU) clock via its DS1/E1 interface.
A network element may have multiple timing reference sources available for generation of a timing signal. Timing circuits often include capabilities to switch to an alternate reference source should the primary reference source fail or degrade to an unacceptable level. It is generally preferable to synchronize a communications system using a timing signal having the highest quality level.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative systems capable of establishing and maintaining a communications timing signal.